FIG. 1 shows a part of a fuse melting type non-volatile memory device proposed in Japanese Patent Application (Patent Application No. 63-204802) filed by the present inventor.
In FIG. 1, a memory cell 12 has a read-only N-channel MOS transistor (hereinafter called N-MOS) 3, an N-MOS 5 for melting a fuse, and a fuse 7 to be melted with current. Such memory cells 1 are formed on a chip and disposed in a matrix shape.
Each N-MOS 3 is formed as having, for example, a channel width 2 .mu.m, a channel length 2 .mu.m, a gate electrode film thickness 4000 .ANG., and a gate oxide film thickness 200 .ANG.. The gate terminal of the N-MOS 3 is connected to a read word line 9. The N-MOS 3 becomes conductive when data is read.
Each N-MOS 5 is formed as having, for example, a channel width 7 .mu.m, a channel length 1.0 .mu.m, a gate electrode film thickness 4000 .ANG., and a gate oxide film thickness 200 .ANG.. The gate terminal of the N-MOS 5 is connected to write word line 11. The N-MOS 5 becomes conductive when data is written.
As the characteristics of the N-MOS 5, the relation between a drain voltage V.sub.D and a drain current I.sub.D is shown in FIG. 2. Referring to FIG. 2, the N-MOS 5 causes a secondary breakdown at a drain voltage about 7 V while a power source voltage (about 5 V) is applied as a gate voltage V.sub.G. Namely, a snap back operation is performed. Under such a condition, the N-MOS 5 can flow a large current in the order of 80 mA. As seen from FIG. 2, the N-MOS 5 has a drain breakdown voltage of about 15 V when the gate terminal is set to the ground potential.
A serial connection of the N-MOS 3 and N-MOS 5 is serially connected between a read data line 13 and a ground wiring 15 connected to ground. The interconnection point C.sub.1 between these transistors 3 and 5 is connected to one end of the fuse 7 whose other end is connected to a write data line 17.
The fuse 7 is made of polysilicon having a thickness 4000 .ANG. same as that of the gate electrodes of the transistors 3 and 5. A narrow melting portion 7a at the center of the fuse 7 has a width 0.8 .mu.m and a length 2 .mu.m. The interconnection point C.sub.1 and a contact area C.sub.2 of the write data line (on the high voltage side of power source lines) 17 each are formed 2 .mu.m.times.2 .mu.m. Thus, the size of the memory cell 1 is about 140 .mu.m.sup.2 (20 .mu..times.7 .mu.) which is a considerably small occupying area.
The write data line 17 to which the other end of the fuse 7 is connected, is connected at its one end to a pad 19. Power is externally supplied via this pad 19 to melt the fuse 7. Namely, a voltage applied to the pad 19 (hereinafter called a melting voltage) is set such that only the N-MOS 5 connected to the fuse 7 to be melted takes the secondary breakdown state. Consider now the case where the fuse 7 (1) of a memory cell 1 (1) is to be melted. In this case, a word line 11 (1) is set to the power source voltage, and a word line 11 (2) is set to the ground potential. As a result, an N-MOS (1) turns on and an N-MOS (2) turns off. Under this condition, a melting voltage is applied to a pad 19 (I). This melting voltage is set to a value lower than the drain breakdown voltage of the N-MOS 5 (2), and higher than the secondary breakdown voltage of the N-MOS 5. Therefore, current flows only through the fuse 7 (1) and not through a fuse 7 (2), melting the fuse 7 (1) as will be described later more in detail.
An N-MOS 20 is connected between the write data line 17 and ground, the N-MOS 20 being turned on and off by a program signal PGM. This N-MOS 20 is made non-conductive by a low level program signal when data is written. On the other hand, when data is read, the N-MOS 20 is made conductive by a high level program signal to set the write data line to the ground potential.
The write data line 17 and the ground wiring (on the low voltage side of power source lines) 15 are made of metal. The read data line 13 is made of polysilicon, n- or p-type diffusion layer, high temperature melting point metal silicide, metal of two-layered structure different from the metal of the write data line 17 and wiring 15, or a combination thereof.
Next, the data read/write operation of the memory cell 1 constructed as above will be described.
First, in operation of data write, i.e., in melting the fuse 7 (1), the program signal PGM takes a low level to make an N-MOS 20 (I) non-conductive. The pad 19 (I) is applied with the melting voltage. Next/ the power source voltage (about 5 V) is applied to the work line 11 (1).
As a result, the N-MOS 5 (1) takes the secondary breakdown state. Thus, a large current flows through a path from the pad 19 (I) write data line 17 (I) fuse 7 (1) to be melted N-MOS 5 (1) ground wiring 15 (I), and to ground. The fuse 7 (1) is therefore melted down. Then, the serial interconnection point C.sub.1 of the selected memory cell 1 (1) is disconnected from the write data line 17 (I) and a write operation is carried out.
Next, the read operation for the memory cells 1 (1) and 1 (2) will be described.
First, the program signal PGM is set to the high level state to make the N-MOS 20 (I) conductive. The read word line 9 (I) is set to the high level state to make the N-MOS 3 (1) conductive. Since the fuse 7 (2) of the memory cell 1 (2) is not melted, a read data line 13 (ii) is grounded via the N-MOS 3 (2), fuse 7 (2), and NMOS 20 (I) to take the low level state. In this state, a low level data is read from the selected memory cell 1 (2).
On the other hand, since the fuse 7 (1) of the memory cell 1 (1) was melted, a read data line 13 (i) maintains to hold the high level state before the read operation. Thus, a high level data is read from the selected memory cell 1 (1).
As described above, in the memory cell 1 shown in FIG. 1, the transistor used for melting the fuse 7 is formed in a MOS type and this transistor is caused to take the secondary breakdown state when the fuse 7 is melted. Therefore, a large current can be obtained with a small channel width. Thus, the transistor used for melting a fuse can be made compact, and the memory cell 1 having a small occupying area can be realized.
Furthermore, since the fuse 7 is melted by a large current, the time required for melting the fuse can be shortened. For example, it is possible to write data in about 0.1 second in memory cells of about 2 K bits.
Still further, in the above-described device, data is written when the electrical characteristics of memory cells are inspected. Therefore, data can be written at the same time without using an apparatus dedicated to data write.
Accordingly, such a memory cell 1 is very suitable for use as a reserved cell of a mask ROM having a redundancy structure. Therefore, by using such a memory cell as a reserved cell, a defective cell of a mask ROM can be replaced by the reserved cell in practical use.
The fuse 7 is melted in a short time by using a fuse melting current I.sub.f of several tens mA or larger. A change of the current before and after melting the fuse 7 is great. Therefore, as seen from FIG. 3, the potentials of a pair of power source lines E.sub.h and E.sub.I oscillate. Namely, noises are superposed upon the pair of power source lines. These noises change not only the potential E.sub.h at the high potential side power source line, but also the potential (ground potential) E.sub.1 at the low potential side power source line. Because of such potential change, the voltage V.sub.E becomes large such as to V.sub.ET1, so it is not rare that the circuit operates erroneously. If a MOS transistor is used particularly for the fuse blow transistor 5, the above described oscillation causes the voltage E.sub.h of the write data line 19 on the high voltage side to become higher than the drain breakdown voltage of the transistor 5, or conversely, causes the voltage E.sub.1 of the ground wiring 15 on the low voltage side to become lower than the threshold value of the gate of the transistor 5, resulting in a malfunction of turning on the transistor 5. Therefore, the fuse 7 connected to the transistor 5 is melted so that an erroneous data is written. The above-described phenomenon occurs within the chip. From this reason, it is very difficult to deal with such a phenomenon using an external circuit of the chip.